1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to an integrated circuit including a plurality of semiconductor memory devices having a stack structure.
2. Description of the Related Art
Semiconductor memory devices have been continuously improved to increase their operating speed according to an increase in the degree of integration of semiconductor memory devices. To increase the operating speed, a so-called synchronous memory device capable of operating in synchronization with an external clock has emerged. The first proposed semiconductor memory device is a so-called single data rate (SDR) synchronous memory device for inputting and outputting one datum in one cycle of a clock through one data pin in synchronization with the rising edge of the clock outside the semiconductor memory device.
The SDR synchronous memory device is insufficient to satisfy the speed of a system that requires a high-speed operation. For this reason, a double data rate (DDR) synchronous memory device using a method of processing two data in one clock cycle has been proposed.
Two data are consecutively inputted and outputted through each of the data I/O pins of the DDR synchronous memory device in synchronism with the rising edge and the falling edge of an external clock. Although the frequency of a clock is not increased, the DDR synchronous memory device provides a bandwidth that is at least twice that of the SDR synchronous memory device, thereby being capable of embodying a high-speed operation that much.
Meanwhile, to operate the synchronous memory device in synchronization with a system clock, several types of new operating concepts that do not exist in the existing memory devices have been added. For example, the several types of new operating concepts include a CAS latency (“CL”), a burst length (“BL”), and an additive latency (“AL”).
The CL refers to the number of system clock cycles until data is externally outputted after a read or write command is inputted to a memory device. The BL refers to the number of data that are consecutively inputted or outputted in response to one data access. The AL is a concept that is newly introduced into a DDR memory device, and it refers to the number of clock cycles from timing at which a read or write command is inputted to a memory device to a RAS to CAS delay (“tRCD”) based on timing at which an active command is inputted. A synchronous memory device consecutively receives an active command, read/write commands, and a precharge command for data access. The AL indicates the advanced input timing of the read/write command defeating predetermined timing.
For example, if AL is 2, an internal read/write operation may be performed after 2 clock cycles since a read/write command is inputted to a memory device. In the case of a synchronous memory device without AL, a corresponding data access operation is performed in response to a read/write command received after system clock cycles corresponding to tRCD since an active command is inputted to the synchronous memory device. On the other hand, in the case of a synchronous memory device with AL, after an active command is inputted to the synchronous memory device, a read or write command is previously received quickly corresponding to AL even if system clock cycles corresponding to tRCD do not elapse.
Accordingly, in conventional semiconductor memory devices, the value of read latency (“RL”) may be represented by the sum of the value of CL and the value of AL. Here, the value of RL is equal to the sum of the value of tRCD and the value of AL because the value of CL is equal to the value of tRCD.
FIG. 1A is a diagram illustrating an AL setting circuit of a conventional semiconductor memory device, and FIG. 1B is a detailed circuit diagram illustrating an AL decoder of the AL setting circuit shown in FIG. 1A.
Referring to FIG. 1A, in the AL setting circuit of the conventional semiconductor memory device, a signal EMRS1P is activated in a case where a mode register is set when a first bank address is received, and signals MREG<3> and MREG<4> are generated by latching external address codes (i.e., setting codes provided by a memory controller) A<3> and A<4> when an MRS signal is activated. Signals EM1REG<3> and EM1REG<4> are generated by latching the signals MREG<3> and MREG<4> in response to the signal EMRS1P. That is, in the mode register setting operation, MRS setting blocks 100 and 110 generate signals to be inputted to an AL decoder 120 by latching the input addresses.
Referring to FIG. 1B, the AL decoder 120 decodes the signals EM1REG<3> and EM1REG<4> and determines the values of AL setting signals AL0, ALCL_1 and ALCL_2 based on a result of the decoding. The decoding method of the AL decoder 120 is shown in Table 1.
TABLE 1EM1REG<4>EM1REG<3>AL000 (AL is disabled)01CL - 110CL - 211Reserved
Referring to Table 1, when both external address codes A<3> and A<4> shift to a logic level ‘L’, and thus both the signals EM1REG<3> and EM1REG<4> are latched to a logic level ‘L’, only the 0th code AL0 of the AL setting signals AL0, ALCL_1, and ALCL_2 is activated to a logic level ‘H’. Thus, the value of AL maintains a value determined when the MRS was previously set or the value of AL becomes ‘0’ so that the value of RL has the same state as the value of CL.
Furthermore, when the signal EM1REG<3> is latched to a logic level ‘H’ and the signal EM1REG<4> is latched to a logic level ‘L’ in response to the external address code A<3> of a logic level ‘H’ and the input address A<4> of a logic level ‘L’, only the first code ALCL_1 of the AL setting signals AL0, ALCL_1 , and ALCL_2 is activated to a logic level ‘H’ so that the value of AL becomes a value in which 1 has been subtracted from the value of CL.
Furthermore, when the signal EM1REG<3> is latched to a logic level ‘L’ and the signal EM1REG<4> is latched to a logic level ‘H’ in response to the external address code A<3> of a logic level ‘L’ and the input address A<4> of a logic level ‘H’, only the second code ALCL_2 of the AL setting signals AL0, ALCL_1, and ALC_2 is activated to a logic level ‘H’ so that the value of AL has a value in which 2 has been subtracted from the value of CL.
Furthermore, when both the external address codes A<3> and A<4> become a logic level ‘H’, the value of AL should become the ‘Reserved’ state so that the value of AL has not been set. That is an operation of setting the value of AL should not be performed. Although not directly shown in the drawing, when the external address codes A<3> and A<4> have a logic level ‘H’ they are not transferred as the signals EM1REG<3> and EM1REG<4> so that all the AL setting signals AL0, ALCL_1, and ALCL_2 are not activated to a logic level ‘H’. Accordingly, an operation of setting the value of AL is not generated. This method of preventing the operation of setting the value of AL from being generated, however, has a danger that may affect the operation of the AL setting circuit itself. Accordingly, as shown in the drawing, even when both the signals EM1REG<3> and EM1REG<4> are latched to a logic level ‘H’ in response to the external address codes A<3> and A<4> of a logic level ‘H’, only the 0th code AL0 of the AL setting signals AL0, ALCL_1, and ALCL_2 may be activated to a logic level ‘H’. Thus, the value of AL maintains a value determined when the MRS was previously set or the value of AL becomes ‘0’ so that the value of RL has the same state as the value of CL. In this method, when the 0th code AL0 of the AL setting signals AL0, ALCL_1, and ALCL_2 is activated to a logic level ‘H’, whether the value of AL will maintain a value determined when the MRS was previously set or whether the value of AL becomes ‘0’ may be determined by a designed.
Meanwhile, in the case of a semiconductor memory device having a 3D structure using a through silicon via (“TSV”), the value of CL must be greater than tRCD due to a cause, such as a TSV load. Thus, assuming that the value of AL is the same, the value of RL of the semiconductor memory device having a 3D structure is greater than the value of RL of a conventional semiconductor memory device. In this case, timing at which the semiconductor memory device having a 3D structure outputs data is slower than timing at which the conventional semiconductor memory device outputs data.
To compensate for this delay, in the case of the semiconductor memory device having a 3D structure, the value of AL should be reduced by the value of CL that has increased due to a cause, such as a TSV load. That is, the value of AL may be able to be set to be smaller in the semiconductor memory device having a 3D structure than in the conventional semiconductor memory device.
The AL setting circuit of the conventional semiconductor memory device shown in FIGS. 1A and 1B does not include a construction for additionally setting the value of AL although the conventional semiconductor memory device has a 3D structure. Accordingly, there is a problem in that the conventional semiconductor memory device may not compensate for the delay.
Accordingly, a conventional circuit for setting the value of AL must be differently configured depending on whether a semiconductor memory device is a common semiconductor memory device or a semiconductor memory device having a 3D structure. This method is very inefficient.